TDCs are widely used for time interval measurements in space science, high-energy physics, laser range finders and test instrumentation. Recently, TDCs have been used for frequency synthesis in delay locked loops (DLLs) for faster acquisition and to avoid false locking. With the advent of digitally-intensive and all-digital phase locked loops (ADPLLs) in deep-submicrometer CMOS, the TDC is becoming an attractive replacement of the conventional phase/frequency detector and charge pump. This also allows to replace the loop filter that requires large and leaky integrating capacitors with a simple digital filter.
Recently, TDC-based frequency synthesizers have been used in fully-compliant Global System for Mobile Communications (GSM)/EDGE transceivers in 90-nm CMOS. The TDC is specifically employed in these transceivers to measure edge time difference between the 1.6-2.0-GHz high-speed complementary clocks (HCLKs) and the 26-MHz frequency reference (FREF) clock.
Typically, the current implementation of TDCs in digital radio frequency processors (DRP) use inverter gates as delay elements and complementary or pseudo-differential D flip-flops to latch the output of the delayed elements. In deep submicron, inverter gates have very short delay (typically about 20 psec) and hence TDC has high resolution. However, the inverting of the polarity across each stage may result in design and layout issues unless extensive layout, matching, corner simulation and lab characterization efforts are undertaken. Such issues include uneven and varying transition times across process, voltage and temperature (PVT) of the rising and falling edges of the delayed clock vector signal and unbalanced metastability resolution of the flip-flops, which can upset the even-odd characteristic of the TDC resolution.
Accordingly, what is needed in the art is a TDC that offers similar timing resolution as an inverter based TDC but without inverting the polarity of the signals.